
	ECE4253 Digital Communications

	Department of Electrical and Computer Engineering - University of New Brunswick, Fredericton, NB, Canada

Linear Recursive Sequence Generator

Shift registers with feedback essentially divide polynomials to create distinctive binary sequences.

This online tool draws and analyzes digital circuits which generate Linear Recursive Sequences (LRS) based on a defining polynomial P(x). The circuit shown below is traced through all possible states. Maximum length sequences are identified. The autocorrelation of each sequence can also be checked (maximum 1023 bits).

Fibonacci Implementation

alternate configuration Fibonacci

Circuit based on P(x) = x⁸+x⁷+x⁵+x³+1

The circuit taps correspond to P(x) = (110101001).

Taps: (110101001) (prime)

Sequence #1 (Starting with 0)

States: 0 0 forever...

Sequence #2 (Starting with 1)

States: 1 128 192 224 112 184 220 110 55 27 13 6 3 129 64 32 144 200 100 178 89 44 22 11 5 130 193 96 176 88 172 214 235 117 58 29 14 135 67 161 208 232 244 122 61 158 79 39 19 137 196 226 113 56 28 142 71 163 209 104 52 154 77 38 147 73 36 146 201 228 114 185 92 174 215 107 181 218 109 182 91 45 150 203 229 242 121 188 222 111 183 219 237 118 187 93 46 23 139 197 98 177 216 108 54 155 205 230 115 57 156 78 167 211 105 180 90 173 86 43 149 74 165 210 233 116 186 221 238 247 251 125 190 223 239 119 59 157 206 103 51 25 12 134 195 97 48 152 76 166 83 169 84 42 21 138 69 162 81 168 212 234 245 250 253 126 63 159 207 231 243 249 124 62 31 15 7 131 65 160 80 40 20 10 133 66 33 16 8 132 194 225 240 120 60 30 143 199 99 49 24 140 70 35 17 136 68 34 145 72 164 82 41 148 202 101 50 153 204 102 179 217 236 246 123 189 94 175 87 171 85 170 213 106 53 26 141 198 227 241 248 252 254 255 127 191 95 47 151 75 37 18 9 4 2 1

Period = 255 (Maximum Length Sequence) (autocorrelation)
Output =
1000000011101100000010011010000011010111000010111100100011100010
1100100100111010110110100111101101110100011011001110010110101001
0111011111011100110000110010101000101011111100111110000010100001
000011110001100010001001010011001101111010101011000111111110100...

See a detailed analysis and State Table for this circuit.

Specify the taps for your sequence

Modulo 2 addition is shown schematically equivalent to Exclusive-OR gates.


2024-04-29 00:30:22 ADT Last Updated: 2014-01-13	Richard Tervo [ tervo@unb.ca ]	Back to the course homepage...